1. Field of Invention
This invention relates to a method for designing a semiconductor device pattern, and particularly relates to a method for designing a stressor pattern of a semiconductor device.
2. Description of Related Art
There has been a method of utilizing a SiGe stressor to form source/drain (S/D) regions of a metal-oxide-semiconductor (MOS) transistor, which utilizes the stressor to control the stress applied to the channel to raise the mobility of electrons or holes and enhance the performance of the transistor.
However, when a computer assisted logic algorithm is utilized to design SiGe patterns and the distance between the SiGe pattern of a PMOS transistor and the active area pattern of the NMOS transistor is set overly small, due to the process variation, the patterned mask layer originally intended to entirely cover the active area of the NMOS transistor cannot entirely cover the same and expose a part of the same.
FIG. 1 illustrates a CMOS transistor in the prior art. Referring to FIG. 1, the CMOS transistor includes a PMOS transistor 10 and a NMOS transistor 18. When the patterned mask layer 16 predetermined to entirely cover the active area 20 of the NMOS transistor 18 does not entirely cover the same, a part of the same is exposed. Hence, in the deposition for forming the SiGe layer 14, an extrusive defect 22 of SiGe grows on the part of the active area 20 of the NMOS transistor 18 exposed by the patterned mask layer 16, lowering the performance of the NMOS transistor 18. In addition, when the SiGe pattern partially overlaps with the dummy diffusion pattern, the above extrusive defect is also formed at the edge of the dummy diffusion region.